1. Field of the Invention
The invention generally relates to a method of selectively forming a semiconductor (germanium) structure within semiconductor manufacturing processes that treats a nitride and oxide surface with a chemical oxide removal (COR) process and then heats and exposes the nitride, semiconductor and oxide surface, to a heated semiconductor (germanium) containing gas to selectively form semiconductor (germanium) only on the nitride and semiconductor surface, but not on the oxide surface.
2. Description of the Related Art
Standard semiconductor manufacturing processes use combinations of deposited, grown and patterned oxide, nitride and semiconductor along with doping and thermal treatments to form transistors which are subsequently interconnected to form integrated circuits. Selectively deposited or grown structures which utilize combinations of oxide, nitride and semiconductors are of great use in semiconductor manufacturing because selectivity enables construction of self-aligned structures and devices which are free of lithography alignment constraints. Examples of self-aligned structures in wide use for semiconductor manufacturing process are spacers, salicide, source/drain implantation, and raised source-drain. An example of a selectively deposited semiconductor is the raised source/drain.
To improve polysilicon gate field effect transistor (FET) device performance, reducing the effective electrical thickness when the transistor is an inversion mode (Tinv) has been one of the key drivers of FET drive current improvement together with shrinking the channel length. Tinv is comprised of two components, gate dielectric thickness and polysilicon depletion thickness. Until recently, Tinv reduction has been successfully pursued by the aggressive reduction of gate dielectric thickness. However, it becomes increasingly more difficult to reduce the gate dielectric thickness below 2 nm because of exponentially increasing gate leakage current from direct tunneling through the thin gate dielectric layer. Increasingly, there is a desire to achieve Tinv reduction by reducing the polysilicon depletion thickness to avoid the increase in gate leakage current from gate oxide thickness reduction. Reducing the polysilicon depletion thickness can be achieved by increasing the concentration of doping in the polysilicon gate. However, in a conventional FET fabrication process, simply increasing the dose of the implanted dopants is problematic because the source/drain is doped at the same time as the gate. When the doping in the source drain region becomes too high, the source and drain diffuse towards each other underneath the gate electrode, creating a high leakage device in short channel FET. Therefore, there is a need for new structures and processing methods to improve the performance of field effect transistors.